Minimizing transistor size in order to keep up with Moore's law continually requires reducing first level interconnect (FLI) pitch and bump size. In addition, using advanced dielectrics has often resulted in utilizing low-k and extremely low thermal conductivity materials in silicon.
The combination of these factors results in higher sensitivity to stress during assembly and thermo-mechanical stress. Therefore, with each new technological advancement, solutions for reducing thermo-mechanical stress become significantly more important.
Stacking chips (CPU, memory, graphics etc.) one on top of one another results in shorter interconnect lines for improved electrical performance (e.g., higher bandwidth and/or lower latency for use in different product segments). However, chip stacking results in increased thermal resistance making it more difficult to remove heat from the CPU relative to non-stacked chips.
Analysis of conventional stacked electronic devices indicates that the thermal resistance of encapsulant layers is the key limiter in transferring heat from stacked packages. Current package architectures use inter-chip encapsulant materials that typically include silica fillers.
The composite thermal conductivity of these typical encapsulants range usually limits the ability of the electronic devices that include the encapsulant formulations to transfer heat from stacked electronic devices.